EDL uses a wide variety of software for computer aided design and simulation. Each design at EDL goes through a rigorous simulation and testing process before it is actually implemented. Shown below are examples from Capture and Pspice, part of the Cadence tool suite, and LabVIEW. Each program can be used in a different way to run simulations on circuits or schematics.
A schematic being drawn in Capture
EDL uses Capture (shown above) to draw schematics. An extension of the program, Pspice (shown below), takes the schematic files and simulates them based on known and assumed characteristics. These programs allow EDL to "test" a design before prototyping it, ensuring a higher-quality finished product.
Output of a simulation in Pspice
After the schematics have been drawn and simulated, the printed circuit boards will be designed using another Cadence tool, Layout.